Imprint lithography is ideally suited for sub-25 nm patterning applications, with sub-3 nm large area patterning demonstrated in research. It offers significant advantages over other lithography techniques, such as self-aligned double patterning (SADP) and directed self-assembly (DSA) in terms of cost and pattern complexity. Recent advances in defect and overlay control in Jet and Flash Imprint Lithography (J-FIL), a specific form of imprint lithography, have set-up J-FIL as a close contender to SADP for manufacturing cost-sensitive devices, such as advanced memory.
One of the ongoing issues with imprint lithography is lower throughput in comparison to photolithography (at least for CMOS devices). Throughput is governed mainly by the area over which overlay can be controlled. J-FIL uses a field size of 26 mm×33 mm to enable mix and match with photolithography scanners. With current overlay techniques, J-FIL can pattern only a single such field in one imprint. This limits the throughput to about 20 wafers per hour.
For single field overlay in J-FIL, eight alignment correctibles are compensated as shown in FIGS. 1A-1H. FIG. 1A illustrates the alignment correctible of the translation in X. FIG. 1B illustrates the alignment correctible of the translation in Y. FIG. 1C illustrates the alignment correctible of rotation (θ). FIG. 1D illustrates the alignment correctible of the magnification in X. FIG. 1E illustrates the alignment correctible of the magnification in Y. FIG. 1F illustrates the alignment correctible of the orthogonality (γ). FIG. 1G illustrates the alignment correctible of the trapezoid in X. FIG. 1H illustrates the alignment correctible of the trapezoid in Y.
Alignment values are obtained at each corner of a field using alignment marks, and are linearly transformed into the eight alignment correctibles (translation, rotation, etc.). The rigid body errors—translation in X, Y and rotation are reduced by the wafer stage. The five scale/shape errors (X Y magnification, orthogonality, and X Y trapezoid) are reduced using the Magnification/Scale Control System (MSCS). Additional details can be found in the work of Cherala et al., “Nanoscale Magnification and Shape Control System for Precision Overlay in Jet and Flash Imprint Lithography,” IEEE/ASME Transactions on Mechatronics, Vol. 20, No. 1, February 2015, pp. 122-132, which is hereby incorporated by reference herein in its entirety.
Unlike photolithography, J-FIL is not fundamentally limited by field size. In fact, whole wafer high resolution imprinting has been previously demonstrated for bit patterned media. But for large area CMOS applications, large area imprinting capability is not enough. It is also necessary to have large area overlay reduction capability, which includes reducing both inter-field (or wafer level grid errors) as well as intra-field overlay errors. In other words, each field in a wafer might have intra-field overlay errors as well as wafer level grid errors. It is currently difficult to independently reduce all of these error components in a multi-field template thereby presenting a challenge to multi-field overlay limiting J-FIL's throughput for CMOS applications.